Via Class Reference
[PIA/VIA]

#include <PiaVia.h>

Inherits PiaVia.

Inherited by RB8506_Via.

List of all members.

Detailed Description

This is the driver for the Parallel Interface module with the the Rockwell R6522 Versatile Interface Adapter (VIA).

A VIA has the following registers:

   Registers       Offset  Rd/Wr   Description
   ------------------------------------------------------------------------------
   PDRB             0      rd/wr   Port B Peripheral Data Register
   PDRA             1      rd/wr   Port A Peripheral Data Register
   DDRB             2      rd/wr   Port B Data Direction Register
   DDRA             3      rd/wr   Port A Data Direction Register
   T1CL             4      rd/wr   Timer 1 counter LSB
   T1CH             5      rd/wr   Timer 1 counter MSB
   T1LL             6      rd/wr   Timer 1 latch   LSB
   T1LH             7      rd/wr   Timer 1 latch   MSB
   T2L              8      rd/wr   Timer 2 LSB, write latch, read counter
   T2H              9      rd/wr   Timer 2 MSB, write latch, read counter
   SR              10      rd/wr   Shift Register
   ACR             11      rd/wr   Auxiliary Control Register
   PCR             12      rd/wr   Peripheral Control Register
   IFR             13      rd/wr   Interrupt Flag Register
   IER             14      rd/wr   Interrupt Enable Register
   PDRA            15      rd/wr   Port A Peripheral Data Register, no handshake

Each of the peripheral data lines (PA0..PA7, PB0..PB7) can be programmed to act as input or output. This is accomplished by setting a "1" in the corresponding Data Direction Register bit for those lines which are to be outputs. A "0" in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input.

Peripheral Data Register: 

   76543210 : data bits 0..7, 0 for low, 1 for high output.

Data Direction Register: 

   76543210 : data direction bits, 0 for input, 1 for output.

Peripheral Control Register (PCR): 

   76543210

   765      : CB2 control; see CA2 control (bits 321)
      4     : CB2 interrupt control; see CA2 interrupt control (bit 0)

       321  : CA2 control
              321 : CA2 input
              3   : 0 : CA2 input
               2  : CA2 active transition for setting IRQA2 flag
                    0 : IRQA2 set by high-to-low transition on CA2
                    1 : IRQA2 set by low-to-high transition on CA2
                1 : independent interrupt
                    0 : CA1 dependent interrupt
                    1 : independent interrupt; see *), IFR

              321 : CA2 output
              3   : 1 : CA2 output
               21 : CA2 output control
                    0x: strobed CA2 output
                    1x: programmed CA2 output with level of bit 3
                    00: CA2 Handshake output
                    01: CA2 Pulse output
                    10: CA2 low
                    11: CA2 high

                 0: CA1 active transition for setting IRQA1
                    0 : IRQA1 set by high-to-low transition on CA1
                    1 : IRQA1 set by low-to-high transition on CA1

Auxiliary Control Register (ACR): 

   76543210 : timer control (not used)

Interrupt Flag Register (IFR): 

   76543210 : what  set                    cleared
   7        : CA2   CA2 active edge        read or write PDRA *)
    6       : CA1   CA1 active edge        read or write PDRA *)
     5      : SR    complete 8 shifts      read or write SR
      4     : CB2   CB2 active edge        read or write PDRB *)
       3    : CB1   CB1 active edge        read or write PDRB
        2   : T2    time out of T2         read T2L or write T2H
         1  : T1    time out of T1         read T1L or write T1H
          0 : IRQ   any enabled interrupt  clear all interrupts

          *): if the CA2/CB2 control in the PCR is selected as "independent"
              interrupt input, then reading or writing the output register
              PDRA/PDRB will NOT clear the flag bit. Instead, the bit must
              be cleared by writing a one into the appropriate bit of the IFR.

Interrupt Enable Register (IER): 

   76543210
   7        : set/clear (reads as "1")
              0 : disable interrupts corresponding to bits set
              1 : enable  interrupts corresponding to bits set
    6       : T1
     5      : T2
      4     : CB1
       3    : CB2
        2   : SR
         1  : CA1
          0 : CA2


Public Member Functions

Construction
 Via (NameCref aName, Addr aAddr=DEF_ADDR, Rack aRack=DEF_RACK)
 constructor; may throw RulbusOpenError

virtual ~Via ()
 destructor (no-op)

Accessors -- port A
int getIrqCA1 ()
 CA1 input: interrupt request pending.

char getEdgeCA1 ()
 CA1 input: get active edge ['p','n'].

int getIntrCA1 ()
 CA1 input: get interrupt enable state.

char getDirCA2 ()
 CA2 i/o: get data direction ['i','o'].

int getLevelCA2 ()
 CA2 i/o: get level [0,1].

Accessors -- port B
int getIrqCB1 ()
 CB1 input: interrupt request pending.

char getEdgeCB1 ()
 CB1 input: get active edge ['p','n'].

int getIntrCB1 ()
 CB1 input: get interrupt enable state.

char getDirCB2 ()
 CB2 i/o: get data direction ['i','o'].

int getLevelCB2 ()
 CB2 i/o: get level [0,1].

Mutators -- port A
void setEdgeCA1 (char edge)
 CA1 input: set active edge ['p','n']; may throw RulbusRangeError.

int setIntrCA1 (int enable)
 CA1 input: enable/disable interrupt.

void setDirCA2 (char dir)
 CA2 i/o: set data direction ['i','o']; may throw RulbusRangeError.

void setLevelCA2 (int lvl)
 CA2 i/o: set level [0,!0]; may throw RulbusContextError.

Mutators -- port B
void setEdgeCB1 (char edge)
 CB1 input: set active edge ['p','n']; may throw RulbusRangeError.

int setIntrCB1 (int enable)
 CB1 input: enable/disable interrupt.

void setDirCB2 (char dir)
 CB2 i/o: set data direction ['i','o']; may throw RulbusRangeError.

void setLevelCB2 (int lvl)
 CB2 i/o: set level [0,!0]; may throw RulbusContextError.


Static Public Attributes

Defaults
const int DEF_ADDR = 0x90
 default rulbus address

const int DEF_RACK = 0
 default rack


Protected Member Functions

Accessors -- port A, B
int getDDRA ()
 Port A: get data direction register.

int getPDRA ()
 Port A: get peripheral data register.

int getDDRB ()
 Port B: get data direction register.

int getPDRB ()
 Port B: get peripheral data register.

Mutators -- port A, B
void setDDRA (int dir)
 Port A: set data direction register.

void setPDRA (int dat)
 Port A: set peripheral data register.

void setDDRB (int dir)
 Port B: set data direction register.

void setPDRB (int dat)
 Port B: set peripheral data register.


Private Member Functions

Mutators -- port A, B
int getIrqC1 (int mask)
 C[AB]1: test for interrupt request pending.

char getEdgeC1 (int shift)
 C[AB]1: get active edge ['p','n'].

void setEdgeC1 (int shift, char edge, char port)
 C[AB]1: set active edge ['p','n']; may throw RulbusRangeError.

int getIntrC1 (int mask)
 C[AB]1: get interrupt enable state.

int setIntrC1 (int mask, int enable)
 C[AB]1: enable/disable interrupt.

Mutators -- port A, B
char getDirC2 (int shift)
 C[AB]2: get data direction.

void setDirC2 (int shift, char dir, char port)
 C[AB]2: set data direction; may throw RulbusRangeError.

int getLevelC2 (int shift, char port)
 C[AB]2: get line level.

void setLevelC2 (int shift, int lvl, char port)
 C[AB]2: set line level; may throw RulbusContextError.


Static Private Attributes

Register offsets
const int OFF_PDRB = 0
 peripheral data register B

const int OFF_PDRA = 1
 peripheral data register A

const int OFF_DDRB = 2
 data direction register B

const int OFF_DDRA = 3
 data direction register A

const int OFF_T1CL = 4
 timer 1 counter low order byte

const int OFF_T1CH = 5
 timer 1 counter high order byte

const int OFF_T1LL = 6
 timer 1 latch low order byte

const int OFF_T1LH = 7
 timer 1 latch high order byte

const int OFF_T2CL = 8
 timer 1 latch high order byte

const int OFF_T2CH = 9
 timer 1 counter low order byte

const int OFF_SR = 10
 shift register

const int OFF_ACR = 11
 auxiliary control register

const int OFF_PCR = 12
 peripheral control register

const int OFF_IFR = 13
 interrupt flag register

const int OFF_IER = 14
 interrupt enable register

const int OFF_PDRA_NH = 15
 peripheral data register A, no handshake

const int ADR_WIDTH = OFF_PDRA_NH + 1
 address with

Shift control bits left for CA/CB
const int SHL_CA = 0
 zero bit shift left for CA

const int SHL_CB = 4
 four bit shift left for CB

Bit masks for CA1/CB1
const int MSK_ATC1 = 0x01
 active transition CA1/CB1 (0:neg, 1:pos)

Bit masks for CA2/CB2: NOTE: Read/Write strobe not supported
const int MSK_DIRC2 = 0x08
 C2 i/o direction.

const int MSK_POC2 = 0x04
 C2 programmed output.

const int MSK_OLC2 = 0x02
 C2 output level.

IFR -- interrupt flag register
const int MSK_IFCA2 = 0x01
 CA2.

const int MSK_IFCA1 = 0x02
 CA1.

const int MSK_IFSR = 0x04
 Shift Register.

const int MSK_IFCB2 = 0x08
 CB2.

const int MSK_IFCB1 = 0x10
 CB1.

const int MSK_IFCT2 = 0x20
 Timer 2.

const int MSK_IFCT1 = 0x40
 Timer 1.

const int MSK_IFIRQ = 0x80
 any interrupt request

IER -- interrupt enable register
const int MSK_IECA2 = 0x01
 CA2.

const int MSK_IECA1 = 0x02
 CA1.

const int MSK_IESR = 0x04
 Shift Register.

const int MSK_IECB2 = 0x08
 CB2.

const int MSK_IECB1 = 0x10
 CB1.

const int MSK_IECT2 = 0x20
 Timer 2.

const int MSK_IECT1 = 0x40
 Timer 1.

const int MSK_IESC = 0x80
 Set/Clear.

The documentation for this class was generated from the following files:
Generated on Tue Oct 12 14:12:06 2004 for Rulbus Device Class Library for Microsoft Windows by doxygen 1.3.4