#include <PiaVia.h>
Inherits PiaVia.
Inherited by RB8506_Pia, and RB8506_Sifu.
A PIA has the following registers:
Registers Offset Rd/Wr Description ------------------------------------------------------------------------------ PRDA 0 rd/wr port A peripheral data register (CRA bit 2 = 1) DDRA 0 rd/wr port A data direction register (CRA bit 2 = 0) CRA 1 rd/wr port A control register PRDB 2 rd/wr port B peripheral data register (CRB bit 2 = 1) DDRB 2 rd/wr port B data direction register (CRB bit 2 = 0) CRB 3 rd/wr port B control register
Each of the peripheral data lines (PA0..PA7, PB0..PB7) can be programmed to act as an input or as an output. This is accomplished by setting a "1" in the corresponding Data Direction Register bit for those lines which are to be outputs. A "0" in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input.
Peripheral Data Register:
76543210 : data bits 0..7, 0 for low, 1 for high output.
Data Direction Register:
76543210 : data direction bits, 0 for input, 1 for output.
Control Register (CRA):
76543210 7 : IRQA1 interrupt flag Goes high on active transition of CA1. Automatically cleared by MPU read of output register A. May also be cleared by hardware reset. 6 : IRQA2 interrupt flag When CA2 is an input, IRQA2 goes high on active transition of CA2. Automatically cleared by MPU read of output register A. May also be cleared by hardware reset. 543 : CA2 control 543 : CA2 input 5 : 0 : CA2 input 4 : CA2 active transition for setting IRQA2 flag 0 : IRQA2 set by high-to-low transition on CA2 1 : IRQA2 set by low-to-high transition on CA2 3 : CA2 interrupt request enable 0 : disable IRQA2 interrupt on active transition of CA2 1 : enable IRQA2 interrupt on active transition of CA2 543 : CA2 output 5 : 1 : CA2 output 43 : CA2 output control 0x: strobed CA2 output (operation of CB2 is not identical) 1x: programmed CA2 output with level of bit 3 00: CA2 Read Strobe with CA1 restore 01: CA2 Read Strobe with E restore (00: CB2 Read Strobe with CB1 restore) (01: CB2 Read Strobe with E restore) 10: CA2 low 11: CA2 high 2 : data direction register access 0 : Data Direction Register selected 1 : Peripheral Data Register selected 1 : CA1 active transition for setting IRQA1 0 : IRQA1 set by high-to-low transition on CA1 1 : IRQA1 set by low-to-high transition on CA1 0 : CA1 interrupt enable 0 : CA1 interrupt disabled 1 : CA1 interrupt enabled
Public Member Functions | |
Construction | |
Pia (NameCref aName, Addr aAddr=DEF_ADDR, Rack aRack=DEF_RACK) | |
constructor; may throw RulbusOpenError | |
virtual | ~Pia () |
destructor (no-op) | |
Accessors -- port A | |
int | getIrqCA1 () |
CA1 input: test for interrupt request pending. | |
char | getEdgeCA1 () |
CA1 input: get active edge ['p','n']. | |
int | getIntrCA1 () |
CA1 input: get interrupt enable state. | |
char | getDirCA2 () |
CA2 i/o: get data direction ['i','o']. | |
int | getLevelCA2 () |
CA2 i/o: get level [0,1]. | |
Accessors -- port B | |
int | getIrqCB1 () |
CB1 input: test for interrupt request pending. | |
char | getEdgeCB1 () |
CB1 input: get active edge ['p','n']. | |
int | getIntrCB1 () |
CB1 input: get interrupt enable state. | |
char | getDirCB2 () |
CB2 i/o: get data direction ['i','o']. | |
int | getLevelCB2 () |
CB2 i/o: get level [0,1]. | |
Mutators -- port A | |
void | setEdgeCA1 (char edge) |
CA1 input: set active edge ['p','n']; may throw RulbusRangeError. | |
int | setIntrCA1 (int enable) |
CA1 input: enable/disable interrupt. | |
void | setDirCA2 (char dir) |
CA2 i/o: set data direction ['i','o']; may throw RulbusRangeError. | |
void | setLevelCA2 (int lvl) |
CA2 i/o: set level [0,!0]; may throw RulbusContextError. | |
Mutators -- port B | |
void | setEdgeCB1 (char edge) |
CB1 input: set active edge ['p','n']; may throw RulbusRangeError. | |
int | setIntrCB1 (int enable) |
CB1 input: enable/disable interrupt. | |
void | setDirCB2 (char dir) |
CB2 i/o: set data direction ['i','o']; may throw RulbusRangeError. | |
void | setLevelCB2 (int lvl) |
CB2 i/o: set level [0,!0]; may throw RulbusContextError. | |
Static Public Attributes | |
Defaults | |
const int | DEF_ADDR = 0x90 |
default rulbus address | |
const int | DEF_RACK = 0 |
default rack | |
Protected Member Functions | |
Accessors -- port A, B | |
int | getDDRA () |
Port A: get data direction register. | |
int | getPDRA () |
Port A: get peripheral data register. | |
int | getDDRB () |
Port B: get data direction register. | |
int | getPDRB () |
Port B: get peripheral data register. | |
Mutators -- port A, B | |
void | setDDRA (int dir) |
Port A: set data direction register. | |
void | setPDRA (int dat) |
Port A: set peripheral data register. | |
void | setDDRB (int dir) |
Port B: set data direction register. | |
void | setPDRB (int dat) |
Port B: set peripheral data register. | |
Private Member Functions | |
Register selectors -- port A, B | |
void | select_ddra () |
Port A: provide access to data direction register. | |
void | select_pdra () |
Port A: provide access to peripheral data register. | |
void | select_ddrb () |
Port B: provide access to data direction register. | |
void | select_pdrb () |
Port B: provide access to peripheral data register. | |
Control ports A/B, C1 (input only) | |
int | getIrqC1 (int offset) |
C[AB]1: test for interrupt request pending. | |
char | getEdgeC1 (int offset) |
C[AB]1: get active edge ['p','n']. | |
void | setEdgeC1 (int offset, char edge, char port) |
C[AB]1: set active edge ['p','n']; may throw RulbusRangeError. | |
int | getIntrC1 (int offset) |
C[AB]1: get interrupt enable state. | |
int | setIntrC1 (int offset, int enable) |
C[AB]1: enable/disable interrupt. | |
Control port A/B, C2 (input and output) | |
char | getDirC2 (int offset) |
C[AB]2: get data direction. | |
void | setDirC2 (int offset, char dir, char port) |
C[AB]2: set data direction; may throw RulbusRangeError. | |
int | getLevelC2 (int offset) |
C[AB]2: get line level. | |
void | setLevelC2 (int offset, int lvl, char port) |
C[AB]2: set line level; may throw RulbusContextError. | |
Static Private Attributes | |
Register offsets | |
const int | OFF_DDRA = 0 |
data direction register A | |
const int | OFF_PDRA = 0 |
peripheral data register A | |
const int | OFF_CRA = 1 |
control register A | |
const int | OFF_DDRB = 2 |
data direction register B | |
const int | OFF_PDRB = 2 |
peripheral data register B | |
const int | OFF_CRB = 3 |
control register B | |
const int | ADR_WIDTH = OFF_CRB + 1 |
address with | |
Bit masks for CA1/CB1 | |
const int | MSK_EIC1 = 0x01 |
enable interrupt on active transition of CA1/CB1 | |
const int | MSK_ATC1 = 0x02 |
active transition of CA1/CB1 if ... | |
const int | MSK_SPDR = 0x04 |
select peripheral data register A/B | |
Bit masks for CA2/CB2: NOTE: Read/Write strobe not supported | |
const int | MSK_DIRC2 = 0x20 |
CA2/CB2 direction (0:in, 1:out). | |
CA2/CB2 input: | |
const int | MSK_ATC2 = 0x10 |
active transition of CA2/CB2 if ... | |
const int | MSK_EIC2 = 0x08 |
enable interrupt on active transition of CA2/CB2 | |
CA2/CB2 output: | |
const int | MSK_POC2 = 0x10 |
CA2/CB2 programmed output. | |
const int | MSK_OLC2 = 0x08 |
CA2/CB2 output level. | |
CA1/CB1, CA2/CB2 interrupt request | |
const int | MSK_IRQ1 = 0x80 |
interrupt request for CA1/CB1 | |
const int | MSK_IRQ2 = 0x40 |
interrupt request for CA2/CB2 |