Registers Offset Rd/Wr Description ------------------------------------------------------------------------------ PDRB 0 rd/wr Port B Peripheral Data Register PDRA 1 rd/wr Port A Peripheral Data Register DDRB 2 rd/wr Port B Data Direction Register DDRA 3 rd/wr Port A Data Direction Register T1CL 4 rd/wr Timer 1 counter LSB T1CH 5 rd/wr Timer 1 counter MSB T1LL 6 rd/wr Timer 1 latch LSB T1LH 7 rd/wr Timer 1 latch MSB T2L 8 rd/wr Timer 2 LSB, write latch, read counter T2H 9 rd/wr Timer 2 MSB, write latch, read counter SR 10 rd/wr Shift Register ACR 11 rd/wr Auxiliary Control Register PCR 12 rd/wr Peripheral Control Register IFR 13 rd/wr Interrupt Flag Register IER 14 rd/wr Interrupt Enable Register PDRA 15 rd/wr Port A Peripheral Data Register, no handshake
Each of the peripheral data lines (PA0..PA7, PB0..PB7) can be programmed to act as input or output. This is accomplished by setting a "1" in the corresponding Data Direction Register bit for those lines which are to be outputs. A "0" in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input.
Peripheral Data Register:
76543210 : data bits 0..7, 0 for low, 1 for high output.
Data Direction Register:
76543210 : data direction bits, 0 for input, 1 for output.
Peripheral Control Register (PCR):
76543210
765 : CB2 control; see CA2 control (bits 321)
4 : CB2 interrupt control; see CA2 interrupt control (bit 0)
321 : CA2 control
321 : CA2 input
3 : 0 : CA2 input
2 : CA2 active transition for setting IRQA2 flag
0 : IRQA2 set by high-to-low transition on CA2
1 : IRQA2 set by low-to-high transition on CA2
1 : independent interrupt
0 : CA1 dependent interrupt
1 : independent interrupt; see *), IFR
321 : CA2 output
3 : 1 : CA2 output
21 : CA2 output control
0x: strobed CA2 output
1x: programmed CA2 output with level of bit 3
00: CA2 Handshake output
01: CA2 Pulse output
10: CA2 low
11: CA2 high
0 : CA1 active transition for setting IRQA1
0 : IRQA1 set by high-to-low transition on CA1
1 : IRQA1 set by low-to-high transition on CA1
Auxiliary Control Register (ACR):
76543210 : timer control (not used)
Interrupt Flag Register (IFR):
76543210 : what set cleared
7 : CA2 CA2 active edge read or write PDRA *)
6 : CA1 CA1 active edge read or write PDRA *)
5 : SR complete 8 shifts read or write SR
4 : CB2 CB2 active edge read or write PDRB *)
3 : CB1 CB1 active edge read or write PDRB
2 : T2 time out of T2 read T2L or write T2H
1 : T1 time out of T1 read T1L or write T1H
0 : IRQ any enabled interrupt clear all interrupts
*): if the CA2/CB2 control in the PCR is selected as "independent"
interrupt input, then reading or writing the output register
PDRA/PDRB will NOT clear the flag bit. Instead, the bit must
be cleared by writing a one into the appropriate bit of the IFR.
Interrupt Enable Register (IER):
76543210
7 : set/clear (reads as "1")
0 : disable interrupts corresponding to bits set
1 : enable interrupts corresponding to bits set
6 : T1
5 : T2
4 : CB1
3 : CB2
2 : SR
1 : CA1
0 : CA2