Registers Offset Rd/Wr Description ------------------------------------------------------------------------------ PRDA 0 rd/wr port A peripheral data register (CRA bit 2 = 1) DDRA 0 rd/wr port A data direction register (CRA bit 2 = 0) CRA 1 rd/wr port A control register PRDB 2 rd/wr port B peripheral data register (CRB bit 2 = 1) DDRB 2 rd/wr port B data direction register (CRB bit 2 = 0) CRB 3 rd/wr port B control register
Each of the peripheral data lines (PA0..PA7, PB0..PB7) can be programmed to act as an input or as an output. This is accomplished by setting a "1" in the corresponding Data Direction Register bit for those lines which are to be outputs. A "0" in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input.
Peripheral Data Register:
76543210 : data bits 0..7, 0 for low, 1 for high output.
Data Direction Register:
76543210 : data direction bits, 0 for input, 1 for output.
Control Register (CRA):
76543210
7 : IRQA1 interrupt flag
Goes high on active transition of CA1.
Automatically cleared by MPU read of output register A.
May also be cleared by hardware reset.
6 : IRQA2 interrupt flag
When CA2 is an input, IRQA2 goes high on active transition of CA2.
Automatically cleared by MPU read of output register A.
May also be cleared by hardware reset.
543 : CA2 control
543 : CA2 input
5 : 0 : CA2 input
4 : CA2 active transition for setting IRQA2 flag
0 : IRQA2 set by high-to-low transition on CA2
1 : IRQA2 set by low-to-high transition on CA2
3 : CA2 interrupt request enable
0 : disable IRQA2 interrupt on active transition of CA2
1 : enable IRQA2 interrupt on active transition of CA2
543 : CA2 output
5 : 1 : CA2 output
43 : CA2 output control
0x: strobed CA2 output (operation of CB2 is not identical)
1x: programmed CA2 output with level of bit 3
00: CA2 Read Strobe with CA1 restore
01: CA2 Read Strobe with E restore
(00: CB2 Read Strobe with CB1 restore)
(01: CB2 Read Strobe with E restore)
10: CA2 low
11: CA2 high
2 : data direction register access
0 : Data Direction Register selected
1 : Peripheral Data Register selected
1 : CA1 active transition for setting IRQA1
0 : IRQA1 set by high-to-low transition on CA1
1 : IRQA1 set by low-to-high transition on CA1
0 : CA1 interrupt enable
0 : CA1 interrupt disabled
1 : CA1 interrupt enabled